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  1. DDS-SIN

    0下载:
  2. 用verilog语言实现DDS的正弦波发送-DDS sine wave sent verilog language
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.51mb
    • 提供者:牛倩
  1. CPU

    0下载:
  2. 设计一个简易cpu,包含指令集,能够实现有限指令的操作,具体见内部文档-Design a simplified CPU that has its own instructions which it can work with.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:2.51mb
    • 提供者:韦壮焜
  1. xapp134_vhdl

    0下载:
  2. The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:2.51mb
    • 提供者:ronsullivan
  1. PLD-LOGIC_SPWM

    0下载:
  2. 电子设计竞赛中获二等奖,在FPGA中实现的两路自然采样SPWM,原理图输入法设计,1024*八位正弦查找表,带FSK和ASK调制功能,频率范围8KHz~12KHz.-Electronic Design Competition second prize in the FPGA to achieve the two natural sampling SPWM, schematic design input, 1024* eight sine look-up table, with FSK and A
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-11
    • 文件大小:2.51mb
    • 提供者:zlz
  1. inv_matrix

    1下载:
  2. 矩阵求逆模块硬件实现,用verilog语言,基于ISE开发环境-implement of inverse matrix
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:2.51mb
    • 提供者:allensmith88
  1. msp430f5529_digital_clock

    0下载:
  2. 这是一份msp430f5529开发板的数字钟例程,实现了数字时时钟,指针式时钟,背光调整等一系列完善的功能-This is a digital clock routine of msp430f5529, it has digital clock, pointer type clock, backlight adjustment and a series of perfect functions
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.5mb
    • 提供者:tanxiaoyao
  1. NFC-for-Mobile-Phones

    0下载:
  2. 在手机设计方案中采用NFC架构和技术的实现方法-The use of mobile phone design in architecture and technology NFC Implementation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:2.5mb
    • 提供者:Shen Fei
  1. response_time

    0下载:
  2. 在fpga开发板上实现一个测试人的反映速度的功能,当灯亮时,按下按键,灯灭,然后数码管显示灯从亮到灭的时间,也就是人的反应时间-In fpga development board to implement a test reflect the speed of people' s function, when lights, press the button, the lamp is off, then the digital display lights from bright to o
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-13
    • 文件大小:2.5mb
    • 提供者:郑大伟
  1. spi_latest.tar

    0下载:
  2. This IP provides specifications for the SPI (Serial Peripheral Interface) Master core. Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.5mb
    • 提供者:qingmingyang
  1. spi_latest.tar

    0下载:
  2. spi接口 verilog版本, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, t
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.5mb
    • 提供者:shen
  1. Libero8.3

    0下载:
  2. 介绍了 Actel FPGA 的集成开发环境 IDE 的使用,从软件的安装和设置,以及 通过一个简单的例子说明如何使用 IDE中集成的第三方软件,如:Synplify、ModelSim等,可以帮助读者快速入门,缩短开发时间。-Actel FPGA introduced the use of IDE integrated development environment, from software installation and setup, as well as through a sim
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-11
    • 文件大小:2.5mb
    • 提供者:anranxjk
  1. spi_latest.tar

    0下载:
  2. 用verilog HDL编写的SPI控制器,从国外网站上找到的。-SPI (Serial Peripheral Interface) is serial, synchronous, full duplex communication protocol. It is widely used as a board-level interface between different devices such as microcontrollers, DACs, ADCs and others.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.5mb
    • 提供者:gsh
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