资源列表
SDI_controller
- 项目:用到FPGA驱动GV7600输出SDI信号，输出分辨率1920*1080p，首先，了解GV7600芯片的特性功能，按照bt1120协议传输10位Y，Cb，Cr数据；其次，我的项目中用的是10位通道分时复用传输Y，Cb，Cr数据；配置引脚很重要，当初verilog代码写好了，因为硬件引脚配置错误，导致调试一直不通；同时，sof文件也要一直更新(Based on FPGA to design the drive controller of GV7600)
multiprocessor
- NIOS 多核例程 调试过 4 cpu NIOS 多核例程 调试过 4 cpu-NIOS-core routine over 4 cpu NIOS debug multi-core debug 4 cpu routines
fpga
- vhdl和c编写，fpga结合单片机完成测频计的功能，fpga主要完成频率的测量并把数据发送给单片机，单片机控制12864液晶完成显示-vhdl and c preparation, fpga of the single chip to complete the function of frequency meter, fpga major to complete the measurement frequency and the data sent to the MCU, MCU contro
FPGAIIC
- 用VHDL和Verilog两种语言编写的I2C总线程序！以调试通过！-VHDL and Verilog with the two languages of the I2C bus program! To debug through!
ADC_Fre_counter_LED_keyboard
- FPGA tlc082０采样控制 高精度测频 ＬＥＤ键盘显示 ＶＨＤｌ 调试与ＥＰ１Ｃ３-FPGA vhdl ADC LED keyboard frequency counter test
spartan3_hdl
- Xilinx Spartan3 library reference.
cpu
- 以ISE为平台设计的单时钟CPU，实现最基本的5条指令（R、LW、SW、BEQ、J） -ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
verilog实现dds
- 基于FPGA实现信号发生器的的功能，较好的参考资料。(The function of signal generator is realized based on FPGA, which is a good reference.)
2440_FPGA
- 在三星2440基础上扩展FPGA,实现多串口通讯的FPGA源码。编译、验证完全正确，放心使用，是不可多得的实用资料！-Based on the expansion of the Samsung 2440 FPGA, FPGA implementation of serial communication source. Compile, verify completely correct, ease of use, is a rare practical information!
Vivado使用教程
- 这是关于VIVADO的使用教程，对于初学者来说，非常有用(This is a tutorial on the use of VIVADO, for beginners, it is very useful)
SPI-Flash
- 基于Xilinx-SPartan 3an FPGA 的与单片机 SPI 接口 参考设计-SPI interface base of Xilinx Spartan 3AN kid