资源列表
and_gate
- verilog code for and gate
controller
- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang Controller (control logic plus state register) VHDL FSM modeling- Simple Microprocessor Design (ESD Book Chapter 3) Copyright 2001 Weijun Zhang C
cordic
- cordic的verilog程序 用ＦＰＧＡ实现
dds
- 是vhdl语言写的dds的部分代码，留下来，方便以后查看-The vhdl language written dds part of the code , to stay , convenient View
fifo.vhd
- fifo Integrated Broadband Electronics
frequency_measure
- 关于用FPGA测量数字信号源频率的源代码。 用的是verilog语言-Measured using FPGA digital signal on the frequency of the source code. Using verilog language
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
multap2
- multiplicador complejos
proje4
- It is 8 bit divisor. it is restoring algorithm implementation.
Gen_R
- FPGA中将用采样点产生相关矩阵R的verilog代码-FPGA will generate correlation matrix R verilog code with the sampling points
mouse_ps2
- vhdl program for ps2 mouse interface