资源列表
cordic
- verilog实现cordic的原理，含详细介绍-verilog to achieve the cordic of principle with details
vhdlclock
- EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
shizhong
- 下面是一个可在开发板上实现的时钟程序,不仅可以做为时钟用,还另外加了个跑秒的功能.-Here is a realization of the development board clock program, not only can be used as clocks, additionally added a stopwatch function.
UART_Transmitter_Arch
- 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages Verilog
lcd1
- lcd display on windows
aFifo.vhd.txt
- Async. FIFO for rtl coding and simulation
gpscode
- coding about gps system
K163_point_multiplication
- elliptic curve in GF2m
Clock
- VERILOG描写的数字时钟，经验证测试通过可以很好地工作！-Digital Clock desinged by verilog,which operates correctly.
fpgadigitalclock
- My thesis entitled \"fpga digital clock,\" immature, to enlighten -My thesis entitled "fpga digital clock, "immature, to enlighten
sfifo
- 该源码是已经通过综合编译，可以直接使用的源码，希望对大家有用。
liangzhu
- 采用verilog hdl设计的音乐播放器，梁祝，在红色飓风2上测试通过。-Using verilog hdl designed music player, Butterfly in Red Hurricane 2 on the test.