资源列表
coding
- FPGA在通信上的运用：基于FPGA的VHDL的HDB3编码-FPGA communications: HDB3 encoding FPGA VHDL-based
MUL_Float_IEEE_754
- IEEE754 floating point mul
vhdlclock
- making a simple clock using altera vhdl
light
- 交通灯控制，别人写的，觉得还不错，分享给大家，希望对大家有用-Traffic light control, written by someone else, I feel pretty good, share with us, we hope to be useful
ptos
- 要求：并行输入1 byte，串行输出，无数据时输出高电平，输出格式1100+8bit+奇偶校验+0011（停止位）串行输入，并行输出，检测是否奇偶校验错误，是否有帧传输错误传输每bit数据占16个clock周期 -Requirements: parallel importation of 1 byte, serial output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial inp
nios
- sample program for up3 education kit
bingchuanzhuanhuan
- 基于Xilinx FPGA ，串并转换模块
ok1
- 用vhdl语言编写的ps2键盘识别程序,并可输出到8*8矩阵显示
LCD1602four
- msp430给553 LCD1602程序，希望对大家有用-msp430 to 553 LCD1602 program, the hope that useful. . .
SDRAM_C
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
存储器模型及测试台
- 512x8存储器模型,及其测试台，用verilog写-512x8 memory model, and the tester, using Verilog write
shizhong
- vhdl描述的数字钟，功能一样，方法不同-vhdl descr iption of the digital clock, the same function, different methods