资源列表
universal_prescalar
- Verilog Code for universal prescalar
priority_decoder
- Verilog Code for priority decoder
seven_segment
- Verilog Code for 7Segment Decoder
VHDL--PCF8563T
- I2C实践，-PCF8563T实时时钟vhdl语言-I2C practice,-PCF8563T real-time clock vhdl language
VHDLfmq
- FPGA驱动蜂鸣器，vhdl语言，蜂鸣器奏乐-FPGA, vhdl language, buzzer music
Verilog-fmq
- FPGA驱动蜂鸣器，Verilog语言，蜂鸣器奏乐-FPGA driver buzzer, Verilog language, buzzer music
Multiplier
- 复用全加器来实现乘法器, 通过从右到左互为输入输出，实现低位计算。最左向高位输出。具体要求请参见附带的PDF。-Multiplexing a multiplier to achieve full adder, input and output by each other right to left, the least significant bits is calculated. Most left output to high. Specific requirements Refer to
Bin2BCD
- FPGA代码，使用Verilog HDL语言实现4 bit二进制转换成BCD代码。原理是移位加三。-FPGA code, using Verilog HDL language is converted into a binary 4 bit BCD code. The principle is Shift-Add-3 .
fft4_T
- 4点FFT处理器设计，流水线式结构。采用状态机，不停地循环。-4-point FFT processor design, pipelined structure. Using the state machine, keep the cycle.
show1234in01
- 基于quartus软件上的多位数码管，可用于显示1234.-Based on the number of digital quartus software can be used to display 1234.
pingpang_ram
- 乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。-Ping pong RAM static random access control, to solve the problem of continuous data flow storage.
CommunicationICdesign
- 通信IC设计的附件里面是通信IC设计这本书各章节的源代码非常详细有利于fpga通信开发-Communication IC design of the annex which is the communication IC design The chapters of the book are very detailed in the source code is conducive to fpga communication development