资源列表
1
- 实现两个乘数为1-3的乘法，输入利用拨码开关控制，输出结果在数码管上显示，编程语言为VHDL-To achieve a multiplier of two for the multiplication of 1-3, the use of dial switch control input, the output results in the digital tube display, programming language for VHDL
verilogsra-1
- SRAM 读写源程序，调试完全可以使用，希望对大家有帮助-SRAM read and write source, debugging can be used, we hope to help
multiplier_n_bits
- VHDL multiplier - input : two n (n customizable) bits width vectors
square_root_n_bits
- VHDL square root - compute square root n (n customizable) bits width vector (restoring square root algorithm)
firfilterPfpga
- FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
verilogiic1121
- I2C通信源代码，调试完可以使用，希望对大家有帮助-I2C communication source code, debugging can be used, we hope to help
pc_fpga_com_latest.tar
- 用VHDL实现的PC与FPGA之间的网络通信，通过以太网进行通信-comunicate between PC and FPGA via ethernet
ps2verilog
- PS2键盘解码源程序，亲测可用，希望对大家有帮助-PS2 keyboard decoding source, pro-test available, we hope to help
arm4u_latest.tar
- DESIGN OF A DYNAMICALLY RECONFIGURABLE PIPELINED RISC PROCESSOR
simple
- FIRST WORD FALL THROUGH FIFO
_MATLAB_AND_FPGA_AlteraVerilog
- 数字通信同步技术的MATLAB与FPGA实现 Altera/Verilog版- U6570 u5B57 u901A u4FE1 u540C u6B65 u6280 u672F u7684MATLAB u4E0EFPGA u5B9E u73B0 Altera/Verilog u7248
DDS
- 四通道DDS信号发生器,Four channel DDS signal generator-Four channel DDS signal generator