资源列表
iprecieve
- udp协议的ipreceive模块，用verilog写的，思路很明确-Udp agreement ipreceive module, written with verilog, the idea is clear
uarttx
- fpga板 verilog写的串口发送数据的模块，主要可以看下思路，也是可用的-Fpga board verilog write serial port to send data module, the main can look at ideas, is also available
Example2
- 基于 VHDL 格雷码编码器设计 格雷（ Gray）码是一种可靠性编码，在数字系统中有着广泛的应用-Based VHDL design Gray Gray code encoder (Gray) code is a reliability of the encoder, it has been widely used in digital systems
Example3
- 含异步清零和同步使能的加法计数器 二进制计数器是应用最多、功能最全的计数器之一，含异步清零和同步使能 的加法计数器的具体工作过程-Including synchronous and asynchronous clear to enable the addition counter binary counter is the most widely used one of the most versatile counter with asynchronous clear and spec
Example4
- 八位七段数码管动态显示电路设计 使用的是两个四位一体、共阴极七段数码管 学习 VHDL 的 CASE 语句及多层次设计方法-Dynamic eight seven-segment LED display circuit design uses two one four, 7-segment LED common learning CASE statement VHDL design methods and the multi-level
Example5
- 数控分频器设计 数控分频器的功能就是当输入端给定不同的输入数据时， 分频器对输入时钟 信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器来设计 完成的，方法是将计数溢出位与预置数装载信号相接得到-NC NC divider divider design feature is that when the given input different input data, the frequency divider with a different frequency di
paobiao
- 使用verilog实现跑表计时功能,已经验证过，能够实现功能-Use verilog to achieve run time function
arinc429_transmitter
- Simple Arinc-429 transmitter channel descr iption on Verilog HDL with parameterized DATA FIFO.
apb_i2c
- Simple realization of I2C interface on System Verilog HDL with support of interrupt generation.
ahb_ebc
- Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
timer
- Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
jtag_slave.4
- 1.1 Compliant with IEEE 1149.1 1.2 Support mandatory BYPASS, SAMPLE/PRELOAD, EXTEST instructions 1.3 Support user register connection beetween TDI-TDO 1.4 Boundary-scan register consist of cell type BC_1