资源列表
reciever
- 通过VHDL语言编写关于8位数码管的8位数据接收器程序。-failed to translate
FPGA-Prototyping-
- Wiley-Interscience - FPGA Prototyping by Verilog Examples - book-Wiley-Interscience- FPGA Prototyping by Verilog Examples- Jun 2008.pdf
VGA2
- VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
vhdl_verilog_tutorial
- Verilog and Verilog tutorial, very good for begginers
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
fir
- FIR filter example for FPGA development
DE2_Default
- Altera DE2 demonstration design, lot of interesting verilog code for synthesis
FPGAtomcs51
- FPGA与51单片机通信接口电路工程文件，非常好用，对于学习VHDL语言的同学们帮助很大。-FPGA and MCU communication interface circuit 51 project files, very easy to use, for students to learn VHDL language of great help.
FPGA-FIR
- FIR滤波器，算法，采用VHDL编程语言，算法比较简单，希望对大家有所帮助。-FIR filter algorithm, using VHDL programming language, the algorithm is simple, we want to help.
ISE-anzhuangjiaocheng
- ISE安装详细说明，包括工程开发流程，测试文件编辑等，包括大量截图，非常适合初学着。-ISE installation details, including engineering processes, testing, editing documents, including a large number of shots, is very suitable for beginners with.
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.
mo12_counter
- 基于FPGA的VHDL程序实现模12计数器-FPGA VHDL model12counter