资源列表
statemation-for-PWM-
- 基于状态机对步进电机的操作,利用VHDL语言编写，在Quartus 8.1环境下测试通过，可以建立波形文件做仿真实验-stepper motor based on ststemation
CRC-Application-Note
- 赛灵思官方发布的关于CRC（循环冗余校验）的设计指导书，对想利用硬件描述语言编写CRC代码的同志很有帮助-CRC Application Note from Xilinx
xapp205_fifo_ctl
- XAPP205 Xilinx FIFO Controller VHDL code
XAPP200_ddr_sdram_64b
- Xapp 200 64 bit DDR SDRAM design files for Xilinx Vertix
buzzer_VHDL
- 实现分频和对音乐的播放，本文件实现对诺基亚铃声的播放，需要配有电路板-To carry out the frequency and music play, this document realization of nokia ringtone playback, need is equipped with circuit board
VHDL-0.1s-Timer
- 该程序完成了在altera de2 环境下实现0.1s新型计时器，该计时器可以运用于广大体育赛事中，有开关、暂停开始键、复位键。-The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
0.01s-Timer-designed-in-VHDL
- 该设计方案是用VHDL语言实现0.01s计时器，该方案列出了详细的开发过程和所有源代码，并虽有仿真结果-The design solution is to use VHDL language 0.01s timer, the program lists the detailed development process, and all source code, and although the simulation results
DE2_SD_Card_Audio
- 这次演示展示了如何执行关于DE2开发- 70板，其中的音乐文件存储在SD卡和董事会可以播放的音乐文件通过其SD卡音乐播放器 CD质量的音频DAC电路。-This demonstration show how to implement an SD Card Music Player on the DE2-70 board, in which the music files are stored in an SD card and the board can play the music fil
alarm
- used to create simple alarm system
Thsign
- 基于VerilogHDL的MTM总线主模块有限状态机设计The MTM bus on the main module VerilogHDL finite state machine design-The MTM bus on the main module VerilogHDL finite state machine design
Altera_Cyclone_III
- Protel99库 Altera_Cyclone_-Protel99 Library Altera_Cyclone_III
Altera_EPCS_Configuration_Device
- Protel99库Altera_EPCS_Configuration_Device-Protel99 Library Altera_EPCS_Configuration_Device