资源列表
fifo89
- 一个先进先出缓冲器的vhdl源代码，深度是8，宽度是9位。-A FIFO CODE IN VHDL.
Block.nonblock
- verilog 中阻塞和非阻塞的电路设计的比较 代码和设计图-Verilog and VHDL block and nonblock design comparison code and layout
4.ripple.counter
- 4位 ripple的寄存器计数器，代码和设计图-4 bit ripple counter code and layout
4bit.lfsr.counter
- 4 bit lfsr 随机数 移位计数器-4bit lfsr counter and layout
brentkung_8
- 8位的brentkung加法器树，在ISE环境下-8-bit brentkung adder tree, the ISE environment
brentkung_16
- 16位的brentkung加法器树，在xilinx软件下-16-bit brentkung adder tree, under the xilinx software
Verilog
- 一个我觉得很不错的课件，讲了Verilog的语言基本要点，和集成电路的一些基础知识-I think a very good courseware, speaking of the basic elements of Verilog language, and some basic knowledge of integrated circuits
multiplier
- 利用Wallace乘法器树原理写的乘法器，6：2的基本单元-Multiplier using Wallace tree multiplier principle of writing, the basic unit of 6:2
deccount16nr
- 16位任意计数分频器,VHDL语言实现,通过测试-Any count 16-bit divider, VHDL language
tracfic
- 这个一个关于交通灯的VHDL程序，有需要的可以下载-The one about the traffic light VHDL procedures, need to download look
spanning_tree_vhdl
- 32-bit spanning tree adder in VHDL
DE2_70_VGA
- 在Quartus中，用de2-70开发板下载实现视频图像处理！很值得认真学习！-In the Quartus in development board with the de2-70 image processing for video downloads! Is worthy of serious study!