资源列表
CPU
- lab peogram CPU on kit Atera. mov/ movi / add/ sub lab 9 + lab 10
P_157
- From Joint stereo to spatial audio coding
A-Simplified-VHDL-UART
- In embedded systems, the processor that we choose for our design may not come with built-in peripherals. Therefore, designers will have to implement these devices in hardware keeping in mind that they will need to interface to the processor. In this
Modelsim
- modelsim命令行的使用方法，基本的命令解释-modelsim command line using the method, the basic command interpreter
AND_GATE
- 执行“与”运算的基本门电路。有几个输入端，只有一个输出端。当所有的输入同时为“1”电平时，输出才为“1”电平，否则输出为“0”电平。-Perform basic gate "and" operation. There are several input, there is only one output. When all the input for the "1" at ordinary times at the same time, the output for a "1" level, o
fengpingqi
- 分频器，输入50MHz,可输出10KHZ，1KHZ，100Hz,10Hz,1Hz.-Divider, input 50MHz, can output 10KHZ, 1KHZ, 100Hz, 10Hz, 1Hz.
modelsim
- 用verilog编写的基于流水线结构的16阶滤波器的实现 -filter
Simple-VHDL-tutorial
- VHDL simple tutorial Farsi
FPGA_Programming
- 介绍FPGA的基本结构、开发流程与Verilog HDL语言基础，并附有加法器、移位寄存器等代码的实现。-Introduce the basic structure of the FPGA development process, and Verilog HDL language foundation, along with the adder, shift register code.
bo-xing-fa-sheng-qi
- 基于fpga的波形发生器 quartus - fpga waveform generator quartus
i2c_VHDL
- VHDL语言编写的I2C总线代码，在quartusII软件编译-Written in VHDL code for I2C bus
CNT60
- 用VHDL设计了60的计数器，并用波形仿真验证了其功能-Design with VHDL counter 60, and a waveform simulation to verify its functionality