资源列表
sin2
- 一个简单的FPGA读取ROM的仿真程序。-A simple FPGA read ROM of the simulation program.
VGA
- 用VERILOG编写的一个可以实现VGA显示的程序-Prepared using a VERILOG VGA display program can .....
i2c
- VHDL接口电路实用源程序，这个是I2C总线通信的。
retiming
- 这篇文章讲述了register retiming技术.这项技术是设计VLSI必须要掌握的技能，另外在基于FPGA设计中，register retiming可以使系统频率上升，提高吞吐量。-This paper describe a register retiming mode for VLSI and FPGA-based design. This mode adopted for design can enhance system throughput and increase system
add
- 介绍了carry_chain_adder，carry_skip_adder,ipple_carry_adder三种常用的加法器，采用verilogHDL语言，利用modelsim软件仿真验证，压缩包中包含有流程图
THANH_GHI_DICH_SANG_TAT
- thanh ghoi dich sang tat vhdl
cctan
- 用VHDL实现的贪吃蛇功能，有蛇，墙，蛇可以上下左右地移动-VHDL implementation of the Snake with the function of a snake, the wall, the snake can move up and down
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
sp605_pcie_13.2
- 基于FPGA，pcie开发的源码程序，已经经过测试，上传来给其他爱好者学习交流。- input user_clk, input user_reset, input user_lnk_up, // Tx input [5:0] tx_buf_av, input tx_cfg_req, output tx_cfg_gnt,
communicationFPGADesign
- 包含matlab和Verilog两中代码：主要功能是关于无线通信的-contain：matlab and Verilog codes about communication
fifo2
- 异步双时钟fifo，vhdl源代码。基本组成是定制的fifo加上空满判断逻辑，基本功能都有-Asynchronous dual clock fifo, vhdl source code. Fifo basic component is a custom air filled with the logic to judge the basic functions are