资源列表
SN7485
- his design is a comparator that compares consecutive bits a0...a3 with b0...b3
base-band_code_generator
- 基于VHDL硬件描述语言的基带码发生器程序设计与仿真，基于VHDL硬件描述语言，产生常用基带码-VHDL hardware descr iption language based on the base-band code generator program design and simulation
jdmfsq
- 基于VHDL硬件描述语言的基带码发生器程序设计与仿真-VHDL hardware descr iption language based on the base-band code generator program design and simulation
PSG
- Altera NIOS II 使用的 AY-3-8910 模組 . 包含 AY-3-8910 Verilog code, SOPC builder使用的hw_tcl及R-2R DAC 電路-AY-3-8910 module for Altera Nios II. verilog source code, hw_tcl file and R-2R DAC schematic.
01_Verilog_Code_my
- different verilog examples
radix2_8fft
- 基2_8点fft运算的程序，带testbench，可以直接仿真使用,程序是分模块设计的。-2_8 point fft program based computing with testbench, you can use the direct simulation.
csa.tar
- opencore ,csa 的vhdl硬件源代码，-opencore, csa of vhdl hardware, source code,
verilog-codes
- bit segmentation in wide division code multiple ace-bit segmentation in wide division code multiple acess
shifter.实现串行数据与并行数据的转换
- 8位双向移位寄存器: 实现串行数据与并行数据的转换,移位寄存数据功能的,8-bit bi-directional shift register: the realization of serial data and parallel data conversion, data storage function of displacement
HS_UJDM
- 硬件描述语言，产生常用基带码，以及实现结果-Hardware descr iption language, producing base-band commonly used code, and the achievement of results
alu[1].eg1
- A 32-Bit ALU Design Example
hw8.rar
- Verilog中经典的自动售货机的源代码，包含测试程序,Vending machine in the classic Verilog source code, including test procedures