资源列表
kvga2
- Nondominated GA for optimization
VGAVesaDdc_pinout_files
- vhdl code for using lcd in an fpga project
JIDAIMA
- 基带码发生器的VHDL源码及仿真程序用于通信系统中基带码的产生
VLSIrtl_spi
- verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.-Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.
Figure_Models
- 用VHDL设计的基本数字逻辑电路，能实现交通灯、模数转换、数模转换等功能-VHDL design using the basic digital logic circuits, to achieve traffic light, ADC, DAC and other functions
BCDADDER
- 一个关于BCDADDR的VHDL实例，对于VHDL语言的学习者很有帮助。-VHDL on the BCDADDR example, for very helpful VHDL language learners.
Electronic-Lock-(VHDL)
- 开锁代码为2位十进制并行码。 当输入的密码与锁内的密码一致时，绿灯亮，开锁；当输入的密码与所内的密码不一致时，红灯亮，不能开锁。 密码可由用户自行设置。 密码可由七段数码管显示出来。 -The design is based on the VHDL language, using the MAX+ plusII parallel electron two locks design, and design process described in detail. VHDL lan
CPU
- CPU VHDL based design
Contador
- counter project developed on the universuty
NAND_Controller_and_ECC_VHDL
- VHDL语言编写，FPGA对nandflash进行读写控制及ECC校验(Written in the VHDL language, FPGA has read write control and ECC check for nandflash)
buffer
- Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA
sha1_latest.tar
- SHA1 消息摘要，一种哈希算法，非常好用(SHA message digest, a hash algorithrim, very useful)