资源列表
Testbenching-Example
- FPGA设计测试用例介绍PPT文档，对于初写测试用例很有帮助。-FPGA Design of test cases to introduce PPT files, helpful for the beginning of writing test cases.
PWM
- pic单片机的脉冲宽度设置程序，虽然程序非常的简单，但是能够自由的调整脉冲宽度-pic microcontroller pulse width of the setup program, although the program is extremely simple, but the freedom to adjust the pulse width
first
- this is useful vlsi ppt explains
Adderloop
- This one is adder loop program using VHDL. And It is help you improve for your VHDL coding ability
mul
- 在gf(2^13)中，固定因子乘法器（基于自然基，0-128）
8bit_mult
- 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
des_Vhdl
- VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
VerilogCodingStylesForImprovedSimulationEfficiency
- This paper details different coding styles and their impact on Verilog-XL simulation efficiency. -This paper details different coding styles and their impact on Verilog-XL simulation efficiency.This paper details different coding styles and their
A3P600-PQG208
- Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 -Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging
FFT
- 用FPGA实现FFT算法,算法实现的可以是基2/4混合基FFT，也可以是纯基4FFT和纯基2FFT运算。
621739486
- 别是需要嵌入的控制数据、相应的字节时钟和数据使能。实现要求：TS流中的空帧很多，将某些空帧（188字节）全换为控制数据DIN（即在该空帧位置处构成一新的数据帧），按照TS流格式进行传输。TS流数据帧中的数据和控制数据不能出现丢失-nothing
can_verilog_source
- verilog code for can controller