资源列表
vhdlcode
- 学习vhdl的学习包，里面有各基本代码，希望对大家有帮助-Learning vhdl learning package, which has the basic code，We hope to help
PCM30_Frame_Sync
- 本程序实现了PCM30的帧同步和失步检测，采用verilog编程，包含了工程文件。-This procedure achieved PCM30 frame synchronization and detection step, using verilog programming, includes the project file.
一些VHDL源代码
- 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
VHDL-Code-For-Full-Subtractor-By-Data-Flow-Modell
- VHDL Code For Full Subtractor By Data Flow Modelling
matlab_code
- 无线通信FPGA设计[田耘等编着][程序源代码]-FPGA design of wireless communication [Tian Yun ed] [source code]
count100
- 用VHDL语言编写的100进制计数器，计数到99后清零-VHDL language with the binary counter 100, count to 99 after the clear
VGA
- verilog的 VGA显示实验-verilog of the VGA display experiment! ! ! ! ! ! ! ! ! ! ! ! !
test1
- 七段译码器的verilog语言程序，功能由七根二极管来显示0到9数字的东西，就是显示器(seven-segment decoder)
计算器3
- 基于51单片机 4*4矩阵 实现简单加减乘除，(The realization of a simple add, subtract, multiply and divide)
8Vx2Y0RDc4Q.js
- ased1325 12412412312 31232131
LCD12864
- VHDL已经在CPLD_EPM240调试OK,,LCD12864显示英文(VHDL has debugged OK in CPLD_EPM240, and LCD12864 shows English)
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)