资源列表
vhdl-digital
- VHD L数字钟 设计源码 包括 设计思想 设计模块 -VHD L source, including digital clock design design design module
seg7
- //奥科单片机网 //www.okmcu.net //CPLD&FPGA实例 //奥科单片机助您成功 //本实验就是学习单个数码管的显示-//Bioko microcontroller network// www.okmcu.net// CPLD & FPGA instance// Bioko microcontroller to help you succeed// this experiment is to study a single digital tube
vgalab1
- VGA_Controller Altrea
freaktm-VHDL-Snake-Game-635ef71
- snake by freaktm. code in VHDL, on Xilinx system
digital-clock
- 电子数字钟，周期为24小时，显示满刻度为23时59分59秒，另外还具有校时功能和闹钟功能-Electronic digital clock, 24-hour period, indicating full scale as 23:59:59, when the school also has a function and alarm functions
Digital_mixer
- This fil eimplement a digital mixer by VHDl and contains a test bench too.
cpld
- 基于CPLD的总线控制逻辑，完全正确经调试-CPLD-based control logic of the bus, completely correct by the debug
EDA2
- 学习数控分频器的设计、分析和测试方法。数控分频器的功能就是当在输入端给定不同输入数据时，将对输入的时钟信号有不同的分频比，数控分频器就是用计数值可并行预置的加法计数器设计完成的，方法是将计数溢出位与预置数加载输入信号相接即可。-NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input th
simple_sin
- The module is a synchronized rom which store the sinc wave in the cell.
VGA DE2
- DE2 VGA
LYZ
- 描述加法器 用vhdl进行性加法器的组合和输入输出-adderDescribe the adder
VHDLstudy
- 近期学习程序小结，对初学者比较有帮助，包括：四D触发器：74175 用状态机实现的计数器 简单的12位寄存器 通用寄存器 移位寄存器：74164 带load、clr等功能的寄存器 带三态输出的8位D寄存器：74374等 -Summary of recent learning process, more helpful for beginners, including: four D flip-flop: 74 175 with a simple state machine im