资源列表
FIFO
- 异步FIFO设计 FPGA代码 Asynchronous fifo-Asynchronous fifo
11_lcd1602
- 这是一个fpga的lcd1602显示的代码，代码是用verilog语言写的，经过编译后成功了，-This is the fpga' s lcd1602 displayed code, code verilog language written successfully compiled,
Pseudo-random
- 伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
12_lcd12864
- 和上面上传的资料一样，这次上传的是12864的显示代码，也是用fpga实现的，当然也是绝对正确的代码-And upload the above information, this time to upload the display code is 12864, is also using fpga, of course, absolutely right code
Divider
- 一个除法器的FPGA代码设计 Divider-fpga Divider
Adder
- 一个加法器的FpGA设计代码 fpga adder-fpga adder
15_tlc5620dac
- 这是芯片tlc5420数字模拟信号传换实验，实验是用verilog语言写的，希望对大家有用-This is the pass the chip tlc5420 digital-to-analog signal change experiment, experiment verilog language written in the hope that useful. . .
13_vga256
- 这是fpga vga显示实验，实验是用verilog语言写的，经过，能够显示，希望对大家有用-Fpga vga experiments is written with verilog language is proven to be able to display the hope that useful. . .
sram_test
- SRAM read/write example
main_i2c
- the complete i2c core written in vhdl and tested on sparten 6 fpga
Digital-clock-design
- 用VHDL语言设计数字钟.实现以下功能：正常走表，时间设置，闹钟设置，整点报时，闹钟提醒。-Digital clock using VHDL language . Achieve the following functions: normal walking table, time settings, alarm settings, the whole point timekeeping, alarm.
parity_chk_32
- 这是一个32位的奇偶校验程序,VHDL代码,可用于FPGA.-32 bit parity check