资源列表
keyboardcontroller_latest.tar
- keyboard controller vhdl
ddslabview
- The reference design and example presented in this article illustrates how you can add a DDS (direct digital synthesis) waveform generator to your LabVIEW FPGA based applicationThe examples for this article are contained in a LabVIEW 8.5.1 project.
CoolRunner
- This the default CPLD design shipped with the board. The CPLD helps reduce the number of jumpers on the board and simplifies the interaction of all the possible FPGA configuration memory sources-This is the default CPLD design shipped with the board.
spislave_latest.tar
- SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.
simple_spi_latest.tar
- SPI主机的Verilog代码，有详细的文档说明。文件无密码！-SPImaster Verilog code, with detailed documentation. No password!
UART
- UART发送数据 中断接受数据 UART发送数据 中断接受数据-UART interrupt receive UART transmit data
am1808_zce_ibis_model_
- 基于AM1808系统开发电路系统产品,电路仿真模型文件-based on am1808 circle design and simulation
ImplementationofaMulti_channelParallelDataAcquisit
- 基于CPLD的并行多路数据采集控制器,包括源代码、测试文件、说明文档。河北大学学报(自然科学版) 2005年 04期 文章“基于CPLD的并行多路数据采集控制器”相应的源代码，作者公开 -Implementation of a Multi_channel Parallel Data Acquisition Controller with CPLD，include source code、testbench and documentation。 source code of the
usb
- USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
TrafficLightControler
- 采用状态机方法设计的交通灯控制器，添加了紧急状态，并且具有时间倒计时显示功能，VHDL源代码-a traffic light controller designed by State machine , a state of emergency is added, and a time countdown display, VHDL source code
FSKPSK
- 基于QuartusII的FSK、PSK实现，完整工程文件，下载就可以运行。-Based QuartusII of FSK, PSK implementation, complete project file, download to run.
Altera
- Altera公司内部培训资料，含有多分权威PDF资料，入门提高一步到位。-Altera internal training materials, the authority of PDF data with multisection, started to improve in one step.