资源列表
CPLD_DEMO_OK
- 可以给VHDL初学者看的实例，全部经过验证-VHDL beginners can see examples of all the proven
clock
- 讲述的是FPGA应用中秒运行的程序，帮助你有效学习开发应用-Tells the FPGA applications seconds of a running program and help you learn effectively develop applications
key.c
- 讲述的是FPGA应用中键盘运行的程序，帮助你有效学习开发应用-FPGA application is about to run the program the keyboard to help you develop applications for effective learning
TestBench_Primer
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-Writing testbench
uart_tx
- quartus.exe 环境下经过编辑和方针之后，作为FPGA器件的实验用串口发送数据驱动。-quartus.exe edited and policy environment after the experiment as the FPGA device to send data using serial port driver.
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
Mesasge1
- generation of message sequence
PNSequence
- pseudo noise generation
SpreadSpectrum
- spread spectrum function proce-spread spectrum function process
priorityencoder
- priority encoder program coding
randwofram
- read and write operations of ram in vhdl
proposal_arv
- this initial stages of research on how to target kalman filters to FPGAs-this is initial stages of research on how to target kalman filters to FPGAs