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  1. nios_sram_gm

    0下载:
  2. 小模式下配置的nios源码,用quartus10.0配置,作者光芒电子-Nios small mode configuration source, with quartus10.0 configuration of the electronic light
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-26
    • 文件大小:8.76mb
    • 提供者:lanmse
  1. 64bitALU

    0下载:
  2. 64 bit alu structure vhdl code -64 bit alu structure vhdl code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.1mb
    • 提供者:chennai
  1. src

    0下载:
  2. 8254 fpga vhdl语言实现代码-8254 fpga vhdl language code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:11.98kb
    • 提供者:日三省吾身
  1. A_VHDL_Timer

    0下载:
  2. 8254计数器fpga实现vhdl语言英文说明文档-8254 counter vhdl fpga implementation language English documentation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:328.51kb
    • 提供者:日三省吾身
  1. vhdl_division

    0下载:
  2. vhdl设计,各种分频方式包括实例,非常实用-vhdl design, a variety of ways, including instances of frequency, very useful
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:411.76kb
    • 提供者:日三省吾身
  1. FPGA_interview

    0下载:
  2. fpga各大公司面试笔试数电部分,内容详尽-number of major companies fpga electrical part of the written interview, detailed
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:24.04kb
    • 提供者:日三省吾身
  1. bit_stuffer

    0下载:
  2. Bit stuffing is used for various purposes, such as for bringing bit streams that do not necessarily have the same or rationally related bit rates up to a common rate, or to fill buffers or frames. The location of the stuffing bits is communicated to
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.01kb
    • 提供者:swapnil
  1. comparator

    0下载:
  2. comparator it comparea two input and give its output
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:1.15kb
    • 提供者:swapnil
  1. randon_numder_generator

    0下载:
  2. random number generator it generate random number continousely on clk pulse
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-23
    • 文件大小:2.54kb
    • 提供者:swapnil
  1. parity_generator

    0下载:
  2. parity generator Parity bits are extra signals which are added to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd num
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:20.44kb
    • 提供者:swapnil
  1. BCD_COUNTER

    0下载:
  2. Binary Counting A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For eac
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:60.67kb
    • 提供者:swapnil
  1. PRIORITY_ENCODER

    0下载:
  2. A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:107.12kb
    • 提供者:swapnil
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