资源列表
assignment_1_part_2
- sample of VHDL coding
clock
- 数字时钟 带数码显示 并且有异步清零的效果-shuzishizhong
T51
- 免费的8051 VHDL 原码。很好的风格。 完整的说明和模拟环境。 实现后的面积很小，速度很高。我比较过这个码与商业的产品， 毫不逊色，在速度上还略有优势。 验证过了串口，输出入口，定时单元及运算单元。 -Free 8051 VHDL source. Good style. Complete descr iption and simulation environment. After achieving the small size of the high speed. I have comp
Audio_DAC_FIFO
- 用于做多媒体缓存的源码 可以做整帧的缓存-SquiDeral- manipulating the cache usage of Your Audio.
fsk_completed
- FPGA为设计载体，VHDL 为设计输入，完成2FSK调制器的实现，下载到DE2平台通过D/A转换模块于示波器上实现-2FSK based on Fpga
mul1
- n*n pipeline multipler
6416_dsk_vhdl
- this file is vhdl file of dsk6416 cpld vhdl file
fp_adder
- this a code for implimenting floating point adder on FPGA -this is a code for implimenting floating point adder on FPGA
PWM_Module
- Very clean design of a PWM module made in structural VHDL. Lower blocks are behavioral.Designed in Quartus 9.0,
filtro_hdlcoder
- Example project of a filter designed in MATLAB and exported to VHDL.
Dip_PB_LED
- 4 bit counter. 1 Push Button (PB) and 1 Dip Switch (DP)are inputs. 4 Leds (common anode) are outputs.
ADC
- analog to digital converson programmed in VHDL