资源列表
parity_chk_32-
- 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
LCD_control
- VERILOG语言编写的LCD1602点阵屏的LCD控制器，用此模块可把MCU省掉，驱动屏幕变简单了-Dot matrix screen LCD controller VERILOG language LCD1602, this module MCU dispense driven screen easier
test
- ISE工程 包含各种基本部件 全加器 寄存器 解码器-The ISE project includes various basic components of the full adder register decoder
5fenpinqi
- 实现5分频的分频器程序，并且使用仿真文件进行测试通过。-5 frequency divider program, and tested through simulation file.
text6_1602
- 1602的VERILOG驱动，希望对你有用！-verilog HDL .v file for LCD1602 display
ss
- 智能车寻迹（PWM调速）和行驶时间显示，VHDL语言编写-Smart car tracing (PWM speed) and travel time
ceshiled
- de2-70上实现led灯流水线闪亮非常好的学习资料-achieve a led lamp pipeline shiny de2-70
usb_test
- altera cyclone 2c35开发板，测试usb通用串行总线,verilog编写的-altera cyclone 2c35 development board test usb Universal Serial Bus, verilog prepared
sram_test
- cyclone 2c35 开发板sram测试的verilog代码。-cyclone 2c35 development board sram test verilog code.
DDR_check
- altera公司cycloneII 2c35开发测试DDR的verilog代码，带仿真波形图。-altera cycloneII 2c35 verilog code development and testing DDR, with simulation waveform.
EP5_PWM_GENERATOR
- PWM信号发生器VHDL源程序+设计思路等等的内容-The contents of the PWM signal generator VHDL source+ design ideas, etc.
equalfreq
- 采用verilog语言实现的等精度频率测量，在FPGA仿真通过-design of Equal precision frequency measurement with verilog HDL in FPGA