资源列表
sequential
- 簡易verilog範例, 初學者容易上手-the simple verilog example, it is easy to starter to learn verilog
FPGAexampledesign
- 参加设计大赛时用的FPGA的例程，应该有很*价值-Participated in the design competition with the FPGA when the routine, there should be a great reference! ! !
ViterbiFPGA
- 探讨了CDMA 数字移动通信中的差错控制问题, 研究用约束度K = 9 的卷积编码 和最大似然V iterbi 译码的差错控制方案. 在V iterbi 译码算法中, 提出了原位运算度量、保 存路径转移过程和循环存取幸存路径等方法, 能有效地减少存储量、降低功耗, 使得K = 9 的V iterbi 译码算法可在以单片XC4010 FPGA 为主的器件上实现, 其性能指标符合CD2 MA 数字移动通信IS 95 标准要求. 文中给出了实测的算法性能, 讨论了FPGA 具体实现
Decoder_3_to_8
- Testbench to generate some stimulus and display the results for the 3-to-8 decoder module
Mux_16to1
- Structural of a 16 to 1 MUX (Sixteen 1-bit inputs) that is built * using two 8-to-1 muxes that feed a 2-to-1 mux
VHDL_Tutorial
- Training VHDL code document
Ver-chap4
- verilog training code document
PerfectTiming
- 完美时序，含中英文两个版本！这应该是FPGA时序分析方面最经典最权威的书了，相信会对FPGA爱好者有很大用处！-Perfect timing, with two versions in English! This should be the most classic FPGA timing analysis the most authoritative book, that would be very useful FPGA lovers!
ISAFPGA
- 一种基于ISA总线的FPGA在线配置方法-A FPGA-based ISA bus line configuration
S3EStarter_ug230
- code VHDL for VGA display
WaveGenerate
- 压缩包里面好友一个word文件，文件介绍了用VHDL语言设计波形发生器-pacage have a word file,introduce the methed to generate wave
wu
- 通信原理基于VHDL的课程设计，基于CPLD_FPGA的数字通信系统建模与设计（通信课设参考书）-VHDL-based communication principle of curriculum design, digital communication system based on CPLD_FPGA Modeling and Design (Communications course design reference)