资源列表
123
- 华为_静态时序分析与逻辑设计，FPGA时序分析友-Huawei _ static timing analysis and logic design, FPGA timing analysis of Friends
mobike
- this a electronic circuit which will control ur motor bike from theft. design is little risky but worth-this is a electronic circuit which will control ur motor bike from theft. design is little risky but worth
i2c_p_altera
- Alter 公司的I2C总线协议 VHDL语言实现 附有详细的说明 可以直接调用-Alter the company of I2C bus agreement VHDL language realization with detailed instructions can directly calls
a_digital_time_keeper1
- 数字时钟 已经在quartus2仿真验证过 VHDL代码-Digital clocks already in quartus2 simulation validated VHDL code
full_duplex_connection_19200_16
- 全双工串口通信VHDL代码 已在quartus2上仿真验证 波特率19200 16倍频-Full-duplex serial communication already in quartus2 on VHDL code simulation validation baud rate 19200 16 octave
lampa_rgb_na_pilota_v1.1
- Lampka rgb na pliota, moż liwoś ć sterowania na odległ oś ć lamoka która ś wieci w kilku kolorach zielony niebieski czerwony-Lampka rgb na pliota, moż liwoś ć sterowania na odległ oś ć lamoka któr
Controller
- Bidirection Counter for an Motor control application
Nios
- Nios2 application baesd project for addition & LED ON-O-Nios2 application baesd project for addition & LED ON-OFF
float01092
- xilinx FPGA中浮点乘法IP核的应用，已通过验证-xilinx FPGA multiply IP
RS232_to_RS485
- RS232_to_RS485 converter on VHDL
CopyCard
- 该程序主要实现多路选择通道。类似于38译码器。-Main achievement of the program multiplexer channels. Similar to the decoder 38.
WirelesscommunicationFPGAdesign.Verilog
- 无线通信FPGA设计[田耘等编著][程序源代码]_2010112514154616，用Xilinx开发，调用modelsim进行仿真。-Wireless communication FPGA design [TianYun, etal] [source code] _2010112514154616, use Xilinx development, call modelsim simulation.