资源列表
first.tar
- 这是我的第一个python程序，哈哈，学着试试玩玩。-This is my first python program, ha ha, try to learn to play.
verilog
- FPGA中verilog语言实现的的USB接口协议，希望能对大家有用-FPGA verilog language in the USB interface protocol implemented in the hope that useful
bintograd
- 二进制转格雷码的程序（verilog)已经过验证-binary to grad
arm7.tar
- this is verilog code for ARM7tdmi,but not supported Thumb .
XHDL3.2.52
- this is a verilog to VHDL tool.
booth1.dir
- booth multiplier in max-plus 10.2
vga
- SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen -SPARTA
VHDL
- 2人抢答器 简易循环彩灯（红灯3s，绿灯2s，黄灯1s） 交通灯-2 Responder simple cycle lights (red 3s, green 2s, yellow 1s) traffic lights
ahblitemaster
- ahb master for single state representation code
code
- nice book and also nice programmme if any body try to understand easily understandable badhu mafat joie che
IntegratedElectronics_MillmanHalkias
- THIS BOOK IS SPECIAL FOR ONE WHO WANTS TO SEE THE DETAILS OF ELECTRONIC COMPONENTS LIKE RESITORS
clock_divider.vhd
- A generic clock divider described in VHDL language