资源列表
tb_gen_mag_comp
- magnitude compararot which is used to comapre the bits
FifoAndTestbench
- 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
SPIVerilog
- 这是一个SPI串行总线接口的Verilog实现-It is a Verilog SPI serial bus interface implementation
SPORT_BUS
- A verilog code for analog devices SPORT bus.-A verilog code for analog devices SPORT bus.
dct01
- Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
Vhdl-IO
- Vhdl method of writing input Output -Vhdl method of writing input Output
CPU
- lab peogram CPU on kit Atera. mov/ movi / add/ sub lab 9 + lab 10
vpi
- showing usage of PLI
iic_verilog
- 完整的IIC MASTER,verilog 的，进过验证的-IIC Master for fpga with verilog
writing-testbench
- 教你如何写VHDL或VerilogHDL的testbench文件，非常有利于FPGA的波形仿真-Teaches you how to write VHDL or VerilogHDL the testbench file, is very conducive to the waveform simulation of FPGA
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
Gate.level.adder
- Verilog 门电路级别的全加器，测试通过-Verilog Gate Level adder and testbenck