资源列表
dds--FPGA
- 基于fpga的dds实现，对应东南大学的ESD试验箱-fpga dds
assignment1
- transistor level stack @ fault model.
Digital-stopwatch-design
- 数字秒表的设计报告，用VHDL语言编写程序，实现分析讨论中各种功能，分别进行编译并生成相应的模块，然后将这些模块连接起来形成电路图，并进行编译、仿真。-Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the correspo
risc
- 16位cpu的各功能模块的源程序，经过FPGA仿真通过，希望能帮到你-16-bit cpu' s each functional module of the source, through the FPGA emulation by, hope you can help
Segment2
- ep2c5 实现 段寄存器 verilog语言，quartus 2 仿真-the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation
S12SPIV3
- this topics is about spi protocol
test3
- 深入浅出玩转FPGA一书中实验中的串口读写实验-Fun FPGA simple terms, a book to read and write from serial com.
ICEEE05---802.11
- This work presents a FPGA design, validation and implementation of an “Orthogonal frequency Division Multiplexing” (OFDM) modulator for IEEE 802.11a using a high level design tool, also reports the resources requirements for the presented system.- T
Quartus
- 用vhdl编写的信号发生器源程序，可以产生正弦波，也可以根据需要产生其他波形-Prepared using vhdl source signal generator can produce sine wave, you can also produce other waveforms as needed
led_liushuideng
- 中途变速且花型丰富的LED流水灯，可直接在源程序里继续添加语句让花型更丰富-Midway variable speed and flowers rich LED light water can continue to add in the source statement flowers richer
baweijiafaqi
- 八位加法器的VHDL程序，可以实现八位二进制数的相加。-Eight adder VHDL program that can achieve the sum of eight binary digits.
shuzihongdianlu
- 数字钟电路的实现，可以24小时计时，可调整时间！-Digital clock circuit implementation, a 24-hour timer, adjustable time!