资源列表
relay-multi-s
- 今天刚买的继电器模块附带资料，文档看不懂，只能看懂图，谁要谁拿去-Just bought today with data relay module, read the document, only read map, who will take you want
DFlipFlop
- 实现双D触发器，已经通过验证，可以实现一般的功能，放心使用-Dual D flip-flop
serial
- 基于VHDL的串口通信 基于VHDL的串口通信-VHDL-based serial communication based on VHDL Serial Communication
LM03806
- LMK03806是一片时钟管理芯片 verilog写的 其中的寄存器设置可能不符合要求 请仔细y阅读文档 已通过仿真-LMK03806 is a clock management chip.This is writed by verilog HDL language,in which the register settings may not meet the requirements.Please read the document carefuly.
NiosII_clock
- 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
_50MHz--1Hz
- 分频电路，可将DE2板子上的50MHz分为1Hz输出，绝对可行，附有仿真程序！-Divider circuit can be divided into the DE2 board 1Hz output on 50MHz, absolutely feasible, with a simulation program!
vhdl-knowlege
- VHDL培训教程，内容浅显易懂，可当做学习课件和教程，简单易学-VHDL training course, the content easy to understand, can serve as a learning courseware and tutorials, easy to learn
hanzigundongxianshi
- FPGA汉字滚动显示 1）用8×8点阵显示屏滚动显示至少4个汉字； 2）可以用拨码开关控制左、右滚动显示。 -Chinese scroll FPGA 1) 8 × 8 dot matrix display with a scroll at least 4 characters 2) can be DIP switch control the left and right scroll.
chuankou
- 串口时序，程序里面的注释内容为同等功能的状态机的写法-Serial port timing, the program content of the comments inside the functional equivalent of a state machine is written
VerilogHDLAD7862
- 运用VerilogHDL实现AD7862的数据采集设计-VerilogHDL achievement of the use of the data collection design AD7862
digital_clock
- 用于FPGA可编程逻辑器件的VHDL语言编写的6显示数字钟程序。51单片机驱动6个LED数码管。-Digital clock (VHDL language) for FPGA Development
74HC283
- 74ls283 基于verilog语言的实现 源程序在压缩包的hdl文件夹中-74ls161 language based on the realization of verilog source package in compressed folder hdl