资源列表
synchronism_design
- 信号进入不同时钟域时的同步处理的例子，请有需要的借鉴参考-Example of the synchronization signal into different clock domains, there is a need to draw reference
fft
- FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。-FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.
stack
- 设计了一个深度为64，字长为16_bit堆栈，要求有栈空、栈满和栈溢出信号。试以双向移位寄存器结构或存储器结构的电路结构方式设计完成电路，并说明它的特点。-Designed with a depth of 64, the word length is 16_bit stack, stack empty, stack full and stack overflow signal. Trial to the way of bi-directional shift register or memory
05_ACA_CS_S10
- this first slide for ACCA-this is first slide for ACCA
SPI_OVM
- OVM based SPI Master checking.
uart_server
- 24路串口转1路串口服务程序, 包括FIFO模块，串口接收，发送模块，定时器模块，检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
EDA-Clock
- 基本功能： 1、输入1KHZ的时钟； 2、能显示时、分、秒，24小时制； 3、时和分有校正功能； 4、当计时器运行到59分49秒开始报时，每鸣叫1s就停叫1s，共鸣叫6响；前5响为低音，频率为500HZ；最后一响为高音，频率为1KHZ； 5、可设定夜间某个时段不报时； 6、设定闹钟。 -Basic functions: input 1kHz clock 2, display hours, minutes, seconds, 24-hour clock 3, hou
sram_5_successed
- 存储器SRAM读写程序，将数字信号存入SRAM-Memory SRAM read and write procedures, the digital signal into the SRAM
1602
- LCD1602液晶屏显示，用verilog HDL实现。-1602 LCD display
adders
- half,full,4,8,10 and 12bit RCA adders
Elevator-automatic-control-program
- 电梯自动控制程序Elevator automatic control programElevator autoElevator automatic control programmatic control program-Elevator automatic control program Elevator automatic Elevator automatic control programcontrol program
proposal_arv
- this initial stages of research on how to target kalman filters to FPGAs-this is initial stages of research on how to target kalman filters to FPGAs