资源列表
teach
- VHDL使用教程很好值得下载共享语法很全面
fequency
- 基于CPLD的等精度数度频率计，可以通过外设功能按键实现，频率、相位、占空比等参数的测量。-CPLD based on the number of degrees of accuracy, such as frequency meter, key peripheral functions can be achieved, frequency, phase, duty cycle measurement of parameters such as
scroll
- 七段数码管显示，可以循环显示一段数字代码，移位速度可由开关控制。本程序可在basys2板子上跑起来-Seven-Segment LED display, you can cycle through a numeric code, the shift speed by switching control. This program can be run up on the board in basys2
dianzheng
- 能在FPGA的板子上实现点阵的功能，利用QuartusII软件-Lattice function, use QuartusII software on the FPGA board
D_Clock
- 数字钟的主要功能有年月日时分秒的显示输出功能和对日期及时间进行设置的功能，还可以有整点报时等功能。设计数字钟的核心问题是时钟日期的自动转换功能。即自动识别不同月份的天数的控制。据此可以设计一个如图１所示结构的数字钟，该数字钟包括校时模块、时分秒计时模块、年月日模块、和输出选择模块。-digital clock is the main function Minutes date when the output function and the date and time set for the f
waterled
- LED3--LED10,由LED10开始循环亮，每1换个灯亮，按SW1就停止跳动，再按一下就继续再跳动-LED3- LED10, from the beginning of the loop LED10 bright lights for every one from another, according to SW1 to stop beating, and then click on the continue beating again
taxi
- 在Quatus下用VerilogHDL语言编写，实现出租车计价器功能
signaltapII_verilogDE2
- This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implement
tut_signaltapII_verilogDE2
- Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in
lcd_1602
- LCD_1602的显示程序 可显示多个数据 但必须是带字库的1602液晶-The LCD_1602 show program can show more data but must take word stock is the 1602 LCD
test-series-10010
- 用于检测序列10010的程序，Verilog的状态机练习-Used to test series 10010 program, Verilog state machine practice
myfifo
- 在quartus II上用宏功能模块编写的fifo先进先出寄存器功能-The fifo first-in, first-out register functions megafunctions written quartus II