资源列表
config_controller
- 用VHDL硬件描述语言实现的对FPGA（Cyclone II）的配置的VHDL源代码。-VHDL hardware descr iption language for FPGA (Cyclone II) configurations VHDL source code.
FPGAJPEGCODING
- motionjpeg的FPGA编码实现，有点老了，但是可以参考．有些东西和h.264是差不多的．-motionjpeg FPGA Coding, a bit old, but the reference. Some things and h.264 is roughly the same.
loop-HELLO
- 8位数码管循环显示HELLO.采用不同的延时时间，让数码管上HELLO,左右显示时的时间不同-8-bit digital control loop shown HELLO. With different delay time on the digital control HELLO, display different times around
dds
- DDS数字式频率合成器 利用VERILOG实现，有modelsim仿真图-DDS digital frequency synthesizer using VERILOG realization, modelsim simulation diagram
onehehe
- verilog设计的4位频率计，可以测量方波、三角波、正弦波；测量范围10Hz～10MHz，测量分辨率1Hz，测量误差1 Hz；测量通道灵敏度50mv
ZHEJIANG_VHDL
- 浙江大学的VHDL讲义，内容翔实丰富，对想掌握这门语言的同学用处极大，我觉得不错，与大家一同分享。-Materials, Zhejiang University of VHDL, rich informative, and would like to master the language the students use great, I feel good to share with you.
chengfaqi
- 基于FPGA采用时序逻辑方法设计的16位乘法器代码-FPGA-based temporal logic designed using 16-bit multiplier code
PicoBlaze_PWM_control_rev1
- This is the Spartan 3E tutorial_04.
hdlc
- 该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation - Codes will be used QUATUSII people should know how to use, in the hop
baweishumaguan
- 利用Verilog hdl语言编写的8位数码管程序，这对于那些刚学Verilog hdl语言的学习者来说，是不错的入门程序，特别程序里头的分频程序模块，谢谢支持。-Using Verilog hdl language of the eight digital control procedures, which for those just learning Verilog hdl language learners, is a good entry procedures, especially
VHDL_Study_zhejiang
- 浙江大学的VHDL中文教程，共127页，PPT课件，是教学和快速入门的重要参考资料
pn
- 基于Xilinx的ISE9.0编译的周期为63的m序列-Compiled based on Xilinx' s ISE9.0 63 m sequence of period