资源列表
vga-display
- 可以让你从最简单的程序中理解fpga如何实现vga时序-to understand how to realize the fpga VGA timing from the most simple procedure
LED_CONCTROLER
- VERILOG语言实现的交通灯控制器,包括工程,源码,及说明文档,对学习很好,已经经过验证.-VERILOG language of the traffic light controller, including engineering, source code, and documentation, to learn well, has been verified.
pulse1
- 分频器 等等大量代码 我测试过 可以-DDS2
test1
- FPGA开发中的数码管显示程序，可显示0~15的十六进制数- FPGA development of digital tube display program, can show the number of 0~15 sixteen
WASH
- VHDL编写的模拟洗衣机程序，能正转20s，暂停10s，反转20s，暂停10s，可能设定要运行的初始时间！-Washing machine simulation program written in VHDL, can forward 20s, pause 10s, reverse 20s, pause 10s, may set the initial time to run!
digicnt
- 带全局复位的1小时倒数计时器。显示在4个7段译码管上，使用48MHz晶振驱动。-1 hour with the global reset countdown timer. 4 7-segment display decoder in the pipe, using 48MHz crystal driver.
EMCSIMoutput
- External SRAM Memory Controller Design Simulation Results
Elevator
- 基于Spartan-3E板的简易电梯控制，采用verilog编写，LCD1602模拟显示电梯状态-Simple elevator control on Spartan-3E board using verilog write, LCD1602 analog display lift status
LED
- LED等循环点亮，verilog实现功能-LED lights light cycle, verilog to achieve functional
Digital6Counter
- 多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa
PN-arraycheck
- 在QuartusII运用ＡＨＤＬ语言，首先设计出PN发生器来产生一个11位的数据流在整个周期内有效数据有 =2047位；再设计状态机用来检测串行数据流中的序列。运用两个个计数器分别对PN码计数以及序列出现的次数计数。改变ＰＮ码结构可以作为通用数列检测器
VHDL_Divider
- 该文档详细介绍了用VHDL语言实现分数分频器和积分分频器，以及50 占空比的奇数分频和非50 占空比的奇数分频。-This document details the odd fractional divider and integral divider, and 50 duty cycle with VHDL divider and an odd number of non-50 duty cycle divide.