资源列表
colorled32
- 这是一个用于32位色控制的LED大屏幕的AHDL代码-This is a used 32-color large screen LED control of AHDL code
ad7862
- 运用VerilogHDL实现AD7862的数据采集设计-using VerilogHDL by AD7862 to collect data
flash
- 本程序代码主要实现的功能是对flash的烧写实验-The code to achieve the function of flash burning experiment
fir_s
- FIR滤波器源代码 以及例化图和波形仿真图-FIR filter source code and instantiated figure and waveform simulation diagram
naozhong
- 一个用vhdl语言编写的可以实现闹钟功能的程序，精确到s-Written in a language with vhdl alarm programs can achieve an accuracy of s
LightsController
- 重庆大学数电课程设计之交通灯（QUARTUS II）-TRAFFIC LIGHTS
UART
- actel 公司 Fusion StartKit开发板串口实验，采用veilog 语言编写，易于理解-actel Company Fusion StartKit development board serial experiments using veilog language, easy to understand
vhdlCompetition.rar
- 用VHDL设计四人抢答器,vhdl学习的基础，很好用,vhdl competition
Serial_Communication
- BJ-EPM240V2实验例程以及说明文档实验之八串口通信-BJ-EPM240V2 experimental test routines as well as documentation of the eight serial communication
modelsim初学者教程
- modelsim的使用教程，一步一步来，很是详细，特别适合初学者。(modelsim use tutorials, step by step, It is very detailed, especially for beginners.)
filter2
- 本实验完成加权均值滤波，其原理如下： 设采集到的数据按节拍输入，依次表示为d0，d1，d2，d3，d4,…，则输出依次为 do= d0*1/4+d1*1/2+d2*1/4 do= d1*1/4+d2*1/2+d3*1/4 … 假设采集到的数据为8位unsigned，输出do只保留整数。-This experiment is completed weighted mean filter, which works as follows: Set data collected
sata_phy_latest.tar
- 用verilog写成的sata2的phy物理层，可应用与sata2的控制层下层接口！-Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!