资源列表
FIRandMATLAB
- FIR数字滤波器的MATLAB设计与DSP实现-FIR and MATLAB
PRINTBMP
- 用于设置显示电脑的SVGA模式，及各个色彩寄存器，来显示输出BMP 图像-to set model of SVGA and register to output the BMP image
12.4Uart
- 最简单的verilog串口发送接收源代码,已经上机调试,请放心,直接使用-Simple transmit and receive serial verilog source code, has been on the machine commissioning, please rest assured, direct use
microwave
- 这是用VHDL语言编译的微波炉控制器的源程序，供大家参考。其中包括扫描显示、计数器等部分。-This is compiled with VHDL, microwave oven controller of the source, for your reference. These include scanning display, counters and other parts.
fifo
- 高性能设计中常用的fifo模型，采用单端读取数据的方式，数据的位宽以及fifo的深度可以设置。通过modelsim仿真-Fifo design commonly used in high-performance models, using single-ended way to read data, the data bit width and the depth of the fifo can be set. Modelsim simulation by
IFFT
- ifft 的verilog程序，最好在ISE9.2的平台上实验-ifft the verilog program, the best experimental platform in ISE9.2
VHDLcircuitdesign
- 《VHDL电路设计技术》，对于VHDL语言爱好者来说是一本很不错的参考资料！欢迎下载！-《VHDL circuit design technology》， VHDL language for lovers is a very good reference! Welcome to download!
FPGA_HuaWei_Verilog
- HuaWei Verilog 约束.rar 华为培训资料，华为工程师讲述FPGA的设计-HuaWei Verilog FPGA
Synplify_FPGA_HUAWEI
- Synplify工具使用指南(华为文档),华为培训资料，华为工程师讲述FPGA软件工具的使用-Synplify of FPGA soft by huawei Inc.
61IC_H8854
- 基于vhdl的 i2c 总线的设计 设计是非常好的 可以用的-jsdkfjsdklfjklasdjfklsd jfl sdjkfkl sdjflsdk jf asdklfjsdklf
uytu
- 89C51连接8255连接矩阵键盘和LED数码管-8255
etester(bk)
- 等精度测频程序，VHDL语言编写，已编译通过，放心使用。-Procedures such as precision frequency measurement, VHDL language, compiled by, ease of use.