资源列表
Virtex-5_FPGA_yonghuzhinan
- Virtex-5_FPGA_用户指南，中文版，详细讲解了Virtex-5_FPGA各个功能-Virtex-5_FPGA_ User' s Guide, the Chinese version of the Virtex-5_FPGA explain in detail the various functional
s3ask_lvds
- S3A LOOP BACK SYSTEM
siqupwm
- PWM的死区控制模块CLK delaywave-PWM control module dead
USB20develop
- cy7c68013结合FPGA的开发笔记，本人原创，FPGA平台是DE2-cy7c68013+fpga develop note
jiaoyong
- 用vhdl实现交通灯的控制 (1) 主、支干道各设有一个绿、黄、红指示灯，两个显示数码管。 (2) 主干道处于常允许通行状态，而支干道有车来才允许通行。 (3) 当主、支道均有车时，两者交替允许通行，主干道每次放行45 s，支干道每次放行25 s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5 s的黄灯作为过渡，并进行减计时显示。 -Vhdl achieved by control of traffic lights (1) main, branch roads, each h
JTAGsoftcoredesignandsimulation
- 关于jtag软核设计与仿真的资料 利用verilog实现，并对仿真进行了说明-Jtag soft on information design and simulation using verilog implementation, and simulation are described
Simple_Verilog_Code_For_Beginner
- verilog code for beginner (adder, comparator, mux, or, and subtractor)
Booth_Multiplier_8bit_Radix_4_With_12bit_Adder_Ko
- verilog code for Booth Multiplier 8-bit Radix 4
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
RGB_YCrCb_Multiplierless_Color_Converter
- verilog source code for RGB YCrCb color converter
ADCData
- ADC Interface to read into FPGA
wangshibo
- 运算器，设计一个4位的算术逻辑单元能够进行下列运算：加法、减法、加1、减1、与、或、非和传递。-yunsuanqi