资源列表
AM
- AM信号的调制解调DSP算法，包括原理和应用-AM
dfilter
- 用FPGA实现信道化接收机算法，共256个信道，处理时钟40M，时分复用完成算法实现-FPGA implementation using channelized receiver algorithm, a total of 256 channels, processing clock 40M, time division multiplexing algorithm to complete
cordic_latest
- it describes the cordic program for trigonometric function-it describes the cordic program for trigonometric function
DA_fir_parrel
- 用FPGA实现并行分布式算法的VHDL程序，采用优化结构实现，功能正确-FPGA implementation using VHDL program parallel and distributed algorithms, realized by optimizing the structure and function correctly
dcm
- Xilinx的V4FPGA数字时钟管理模块的底层原语实现代码，硬件上跑通- The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
i8255
- 8255的VHDL仿真实现的是串并接口的功能-8255' s VHDL Simulation is the string and the function of the interface
ITI932x
- 这是ILI9320的液晶屏驱动程序，是FPGA的驱动程序用nios ii编译的-This is ILI9320 LCD screen driver is the driver FPGA compiled by nios ii
keyboard
- 矩阵键盘扫描接口，使用Verilog编写-keyboard writed in Verilog
UART
- uart接口，使用Verilog编写，适用于各类FPGA-uart interface written using Verilog, applicable to all FPGA
VGA
- VGA彩条信号发生器，使用Verilog编写-VGA color bar generator, written using the Verilog
DDS
- 数字频率计 DDS，使用Verilog编写-Digital frequency meter DDS, prepared using the Verilog
ASKencoderanddecoder
- ASK编码器与译码器，使用Verilog编写-ASK encoder and decoder, the use of writing Verilog