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  1. xiao

    0下载:
  2. 四选一选择器的verilog实现!希望有用-Four selected to achieve a selector verilog! Hope that useful
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:191.81kb
    • 提供者:cj
  1. keypadinterfacecontroller

    0下载:
  2. 设计并实现一个4X8键盘接口控制器,含有时序产生电路、键盘扫描电路、弹跳消除电路、键盘译码电路、按键码存储电路、显示电路。要求:当按下某一键时,在数码管上显示该键对应的键值-Design and implement a 4X8 keypad interface controller, with timing generator circuit, the keyboard scanning circuit, bounce elimination circuit, the keyboard deco
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:6.03kb
    • 提供者:zhuimeng
  1. calendar

    0下载:
  2. 一个简单的日历子系统,有闰月检查,非常简单-A simple calendar subsystem
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:545byte
    • 提供者:绿竹小子
  1. SystemVerilogAssertion

    0下载:
  2. SystemVerilog Assertion的应用例子。例子均在Synopsys VCS环境下编译通过。-The uploaded files are examples of Systemverilog Assertions. All of the codes are compiled successfully in Synopsys VCS environment.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5.41kb
    • 提供者:ls
  1. snake

    0下载:
  2. 在数码管上跑的贪吃蛇Verilog 程序-In the digital Verilog programs run on Snake
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:672byte
    • 提供者:绿竹小子
  1. sm

    0下载:
  2. This example shows how a Sm component is directly coded in VHDL as concurrent statements. The multiplexor is coded as a single "when" statement. "Sm" is mnemonic for subtractor-multiplexor.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-24
    • 文件大小:298.38kb
    • 提供者:Gopi
  1. lab_instructions1

    0下载:
  2. The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:1.13mb
    • 提供者:Gopi
  1. lab_instructions2

    0下载:
  2. The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-10
    • 文件大小:2.14mb
    • 提供者:Gopi
  1. lab_instructions3

    0下载:
  2. The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1023.95kb
    • 提供者:Gopi
  1. Spartan-3ADSPs

    0下载:
  2. The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.-The objective of the labs today is
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1016.22kb
    • 提供者:Gopi
  1. keyboard

    0下载:
  2. 键盘功能的实现,主要用来显示键盘上所恩下的键对应的数字-keyboard
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:560.72kb
    • 提供者:num1
  1. duogongneng

    0下载:
  2. 多功能波形放生器,产生三种波。方波。。j锯齿波。。正弦波 -Release device function waveform, resulting in three waves. Square wave. . j ramp. . Sine wave
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:7.34kb
    • 提供者:唐忠
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