资源列表
VerilogHDLlianxiti
- 所上传的材料是关于FPGA的VERILOG语言的-VERILOG
KCSJ
- 简单的错误检测VHDL编程，有助于初学者-Simple error detection VHDL programming, help for beginners
vhdl
- 检测一组或多组又二进制码组成的脉冲序列信号，当序列检测器连续收到一组或多组序列信号，如果与预先设置的码相同的时候，输出1，否则输出0. -Detection of one or more group was composed of binary code pulse train signal, when the sequence detector continuous sequence of one or more groups received signal, if the same co
sdsdsd
- Cpu 8bit. Vorks good. Taking all instructions, sdo OR Xor and athor... Is registers
Verilog
- 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
new
- four bit shift register verilog code-four bit shift register verilog code
shift_register
- It is noise generator.it is a linear feedback 16 shift-registe where the bits 15,14,12,3 are fed back via xor gates.make random signal close to real noise
seven_segment
- It is seven segment decoder and display hexadecimal digits, and for wirting with vhdl use PACKAGE-It is seven segment decoder and display hexadecimal digits, and for wirting with vhdl use PACKAGE...
memory
- DESIGN A SINGLE PORT MEMORY 8*256 using array with standard logic & tri_state gate, and simulate it by reading & writing word
alu8bit
- it implement alu for 8 bit addition,subtraction,and ,or, left shift without overflow support and simulate it in modelsim
FinitStateMashine
- implement finit state machine for finding "1010" pattern in a bit stream,there might be several after each other and also use one-hot state in modelsim
shuzimiaobiao
- 秒表设计中的分块模块的设计，运用VHDL语言编写-Stopwatch design block module design, the use of VHDL language