资源列表
Pertama
- Simple decoder Design synthesized and loaded to board
cb
- 实现串并转换，非常好用的，已经经过仿真验证的，可以通过。-String and convert to achieve, very easy to use, has been verified by simulation, you can.
zhengxuanbo
- 产生正弦波的vhdl代码，输出显示波形标准，没有明显的波形失真。-Vhdl code for sine wave generation, the output waveform standards, no significant waveform distortion.
a_vhd_16550_uart_latest.tar
- it ia uart with all the features in it.
vote
- 当表决器的七个输入变量中有4个以上（含4个）为“1”时，则表决器输出为“1”；否则为“0”。分析七人表决器全加结果CBA（从高位到低位）中的八种情况：000-111，输出为“1”的量为100-111, 根据这种真值表用卡诺图化简可得出最简逻辑表达示为OUT=C，即全加结果最高位决定了结果。-failed to translate
Zet-1.2.0
- 在DE1开发板上运行Windows系统，编写语言是Verilog-failed to translate
uartin
- 串口通信，实现数据的串并转换，以及并串转换-Serial communication, serial and parallel data conversion, and parallel to serial conversion
rea_wri_ram
- 用FPGA实现对RAM的读写，实现特定的功能-FPGA implementation of the RAM with read and write, to achieve a specific function
simulator_PCI
- about PCI connection in Quartus
jnsn
- vhdlcode for a johnson counter-vhdlcode for a johnson counter
lcd_verilog
- varilog code for LCD based
Andor
- 与或门的实现的小程序，用VHDL语言编写而成的源代码-failed to translate