资源列表
25LC512
- 25LC512 512K-BIT SPI SERIAL EEPROM (VCC = +2.5V TO +5.5V) 的模型和文档。-25LC512 512K-BIT SPI SERIAL EEPROM (VCC =+2.5V TO+5.5V) behavioral model and datasheet.
new_triangle
- verilog HDL长生三角波，很简单的程序，大家可以看看，互相学习一下！
spwm_gen
- 正弦脉宽调制SPWM波的产生VHDL代码与相关IP核产生与说明，-Nuclear generation and descr iption of the sinusoidal pulse width modulation SPWM wave generated VHDL code and related IP
I2C
- I2C总线源码，用于I2C总线编程设计-I2C bus source code for I2C bus programming design. . . .
Use-FPGA-24KHZ-27KHZ-sine-wave
- 使用FPGA产生24KHZ到27KHZ的正弦波，步进为20HZ，可以通过按键调节-Use FPGA to generate a 24KHZ 27KHZ sine wave, stepping 20HZ, key adjustment
cdromsrc
- Verilog HDL应用程序设计实例精讲的书籍光盘代码-Books CD-ROM code Verilog HDL application design example 精讲
I2C_TEST
- verilog写的AT24C02的连续读和连续写，供大家参考-verilog write AT24C02 sequential read and written continuously, for your reference. .
LSY_wave
- 比赛时写的李萨如波形发生器的代码，用verilog写的，里面集成数据采集和DDS波形发生。-Game when writing the the Lissajous waveform generator code, written in verilog the inside integrated data acquisition and DDS waveform generation.
16_MUX
- AM2901 Benchmark - test patterns for output shifter-AM2901 Benchmark- test patterns for output shifter
display
- display_stim.vhdl Testbench for display Benchmark
scan2
- 数码管扫描显示，两位数码管显示，当扫描频率高时就是静态显示。-Digital the tube scan display, two digital tube display is a static display, high scanning frequency.
my_half_add
- 基于FPGA的半加器源码，声明，有verilog编写的-FPGA-based half adder source, statement, written in verilog