资源列表
EDA
- VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
sv
- stack and events in system verilog
LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com)
- LCD Driver And Keyboard char Asm(www.bargh20.com)
7_DynDigTub
- FPGA，VHDL语言动态显示一位数码管，使用所有FPGA芯片，课重新分配引脚-FPGA, VHDL language dynamically display a digital tube, all FPGA chip, the lesson reallocate pin! !
2_KeyLED
- FPGA，VHDL语言 用按键点亮一个灯，适用于所有FPGA芯片，可重新分配引脚-FPGA, VHDL language with the keys lit a lamp, applies to all FPGA chip and can reallocate pin! !
9_TheBell
- FPGA，VHDL语言 蜂鸣器 响0.5S~~，时钟分频源程序，适用于所有FPGA芯片-FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
1_Lit_OneLED
- FPGA，VHDL语言，静态点亮一个LED，VHDL源程序~~~Quartus II软件-FPGA, VHDL language, static light a LED VHDL source code ~ ~ ~ applies to all FPGA chip! ! !
Proj
- 读AD数据后，写CF卡控制，可调整采集速率和存储速率-AD data is read, write CF card control, adjustable acquisition rate and storage rate
2025L
- 2025驱动程序很好用的很难找的我们找了好久才找到的希望对大家有帮助-The 2025 driver good with hard to find we are looking for a long time to find the hope to help
LFSR_FIFO_GasP
- • LFSR uses global clock > Every stage contains valid data > Data moves in lock-step > Bit sequencing and synchronization implicitly enforced • Async implementation requires explicit control > Not every stage contains
DVB
- This for the symbol interleaver. Wire permutation and the symbol intrleaver are present here.-This is for the symbol interleaver. Wire permutation and the symbol intrleaver are present here.
shift_arr
- This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.