资源列表
bfgd_fpga
- 实现了ARM9的数据采集与存储，使用主板是EP9315，是FPGA的控制部分，代码全。-ARM9-implemented data collection and storage, the use of the motherboard is the EP9315, the control section is the FPGA, all the code.
DDS_Adder
- DDS加法程序，用verilog程序写成，在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s
pong_bats
- 用Verilog语言描述乒乓球游戏，并借助VGA平台进行显示，该游戏可以实现乒乓球的变速，并实现计分的功能-it describes Pingpang Game
alarm
- 用Verilog语言描述一个定时器的设计，该定时器具有闹表，定时，和正常时间显示的功能- It designs a clock by Verilog
edit4_16
- 4-16译码器,实现4位至16位的译码功能,类似于3-8译码器,通过时序验证.-4-16 decoder to achieve 4-16 in the decoding functions, similar to the 3-8 decoder, through the timing verification.
CNT10
- 十进制计数器,实现异步复位,同步清零功能, 方法简单易行,通过时序验证.-Decimal counter, asynchronous reset, synchronous clear function, simple and easy, by timing verification.
SHFRT1_4
- 4位并入串出移位寄存器,实现并串转换,简单易行,通过时序验证.-4-bit shift register into the string out to achieve and string conversion, simple, through sequence verification.
4_2
- 4位二进制加法计数器,实现简单的加法功能,最高支持4位,用二进制形式计算.-Counter 4-bit binary addition, addition of simple features, up to 4, with binary calculations.
eit8_3
- 8-3译码器,实现3-8译码器的逆功能,简单易行,已通过时序验证.-8-3 decoder, to achieve the inverse function of the decoder 3-8, simple, has passed the timing verification.
8255_HDL
- 8255为常用的接口类型。该代码主要描述用硬件语言实现8255并行接口，-it mainly describes how to finish a 8255 by HDL
edit16_4
- 16-4编码器,实现16位转4位的编码,是4-16译码器的逆程序,通过时序验证-16-4 encoder to achieve 16-bit to 4-bit code, is the inverse process decoder 4-16 through the timing verification
COUNTER32B
- 32位移位寄存器,实现具体右移功能的32为寄存器,结构简单,通过时序验证-32-bit shift register 32 functions to achieve specific right to register, simple structure, through the timing verification