资源列表
LCM_display
- （3）实验3：LCM显示实验，完整的设计工程文件在LCM_display文件夹下-(3) Experiment 3: LCM display experiment complete design engineering the file in LCM_display file folder
Key_interrupt
- （4）实验4：按键中断实验，完整的设计工程文件在Key_interrupt文件夹下-(4) Experiment 4: Key interruption experiments, complete design engineering files in Key_interrupt file folder
count_display
- 5）实验5：计数显示实验，完整的设计工程文件在count_display文件夹下-5) Experiment 5: count display experiment, a complete design engineering files in count_display file folder
RS232
- （6）实验6：串口通讯实验，完整的设计工程文件在RS232文件夹下二、运行环境 程序在以下环境调试通过： （1）Windows XP； （2）Altera公司的Quartus II 8.0 for windows； （3）Altera公司的Nios II 8.0 IDE for windows； （4）Mentor公司的ModelSim SE 6.0；-(6) (2) Altera Corporation Quartus II 8.0 for windows Exp
Flash
- （7）实验7：外部FLASH扩展实验，完整的设计工程文件在Flash文件夹下-(7) Experiment 7: the external FLASH expansion experiments complete design project files in the Flash file folder
pwm_custom
- （8）实验8：添加用户组件外设实验，完整的设计工程文件在pwm_custom文件夹下 -(8) Experiment 8: add user components peripherals experiment, a complete design engineering files in pwm_custom file folder
LL
- verilog语言描述的SDRAM程序代码。-verilog language to describe the the SDRAM procedure code.
LL
- verilog语言的异步接口转换设计程序代码.-verilog language the asynchronous interface converter design code.
LL
- verilog语言的计数器设计程序代码。-counter verilog language design code.
LL
- verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
VGA_control
- 介绍用VHDL实现vga控制的原理及方法，并提供了一个实例-Introduced the use of VHDL realization of a vga control principles and methods, and provides an example
hfjhtb
- 整个ofdm系统的每一步功能的verilog实现-The ofdm system as a whole every step functions verilog implementation