资源列表
codigo-fuente-rxbot
- rxbot latest version
ddr_verilog
- DDR控制器的VERILOG代码；状态机；读写；刷新等操作-ddr controller,verilog
extension_pack_latest.tar
- This project contains files you can use to expand upon the basic IEEE packages you normally use for creating testbenches and RTL code. Automatic count stop/start value generation functions. You enter a time duration and clock frequency and the v
mean-simulation
- 一个均值仿真的代码！真的很好！完整的工程文件-A mean simulation code! Really good! Complete project file
add_led
- 利用K1,K2来代替A2 A1 的数据输入。 利用K3,K4来代替B2 B1 的数据输入。 我把A0和B0都设置成1了。 所以一开始数码管显示的是E.应为111加111就等于E 数码管显示相加结果-K1, K2 to replace A2 A1 data input. K3, K4 to replace B2 B1 data input. A0 and B0 are set to 1. So beginning digital display E. should be 111 p
jiafaqi
- 利用FPGA，VHDL设计一个加法器控制LED。-The use of FPGA, VHDL design an adder control LED.
FPGA_DS18B20
- 利用FPGA，vhdl语言设计，控制DS18B20芯片温度检测。-FPGA, vhdl language design, control DS18B20 chip temperature detection
Simply-RISC-M1-Core.tar
- Simply RISC M1 Core.tar
minimips_latest.tar
- minimips MIPS CPU源码，包括文档说明-minimips CPU source code documentation etc
axi_master_latest.tar
- RobustVerilog generic AXI master stub源码，包括文档说明-RobustVerilog generic AXI master stub
sdram
- 自己做的一个SDRAM控制器，供大家参考啊！-Own a SDRAM controller for your reference!
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit