资源列表
ASK_modulator
- 振幅键控ASK的调制解调Verilog实现，带测试文件-ASK amplitude shift keying modulation and demodulation Verilog implementation, with the test file
BPSK
- 八相移键控调制的Verilog程序，给出了各个子模块的程序，实现了信号调制。-Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.
spartan3e_picoblaze_timer_LCD
- 基于spartan3e sdk的时钟与LCD实验项目。-Based on spartan3e sdk and LCD clock experiments
uartverilog
- FPGA串口通信，已在FPGA实验板上用串口调试助手实验成功，可以硬件实现。-FPGA serial communication experiment was a success in the FPGA board serial debugging assistant, can be implemented in hardware.
ledwater
- 流水灯实验，本代码仅供交流学习，未经同意不得用于其它商业用途。-ke yi zhuanzai
speed_measure_on_7_segment
- Period method of frequency measuring (change constant to speed measure). DE2 Board Quartus project. Input signal on GPIO, result on 7seg, start/stop with key[0].
Zed_vga_hdmi_720p
- 开发板zedboard上的hdmi的显示，采用开发工具ise，熟悉ideo的时序，推荐给大家-Hdmi display board zedboard on using development tools ise, familiar ideo timing and recommend it to everyone
micron-lpddr-sdram-lpddr_model
- modelsim，micron公司的ddr sdram仿真模型，verilog。-modelsim，micron，ddr sdram simulat module，verilog。
4bit-adder_verilog
- 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
seg
- verilog编写的时钟分频程序和数码管显示程序-verilog
VGA
- 基于VHDL语言和Altera cycloneII实验平台的VGA实验，希望对初学者有所帮助-VHDL language and Altera cycloneII based experimental platform VGA experiment, hope to help beginners
HMM
- 有关HMM的MATLAB代码 都在压缩文件了-CODE FOR HMM DOWNLOAD WHEN YOU NEED