资源列表
UART_IP_core_for_wishbone
- 基于wishbone总线的UART IP core-UART IP core based on Wishbone, generated in Verilog HDL.
decl7s
- 共阴极七段数码管的译码程序，用VHDL程序编写-Seven-Segment LED common cathode of the decoding process, and VHDL programming
deccount2.5
- 2.5分频器设计,用VHDL编写-2.5 divider design using VHDL
adctest
- avr单片机自带的adc转换，并能把转换结果打到电脑上进行显示。-avr microcontroller comes with adc conversion, and conversion results can be displayed on the computer hit.
VHDL
- 利用VHDL实现任意函数发生器，包括方波、正弦波、三角波等。-The use of VHDL to achieve arbitrary function generator, including square, sine wave, triangle wave and so on.
LCDCharacterDisplayExperimentC51Version
- LCD字符显示实验C51版本，液晶显示屏的现实控制程序-LCD character display experiment C51 version of the reality of LCD control procedures
six_smg2
- 六个数码码动态扫描接口程序，用VERILOG语言编写的
ref-sqroot
- 这是用于VHDL的开方运算，大家试试看，能不能好用-sqrt
time-of-clock
- 单片机中实现一个时钟的代码可以设置定时时间，-dan pian ji zhong shi xian yige shi zhong de daim a
ref-sqroot
- 開平方根IP將sqroot_license.txt中的FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING=gl15kdhm5gUPkJD7iM82mn$$ HOSTID=ANY加入就可以使用了！
AXI_VIP
- axi vip code used in almost all the interface projects in the soc and verification environments in arm processors
veriloghomework
- 清华大学的verilog作业，里面有相应的例子和答案，作为练习相当的不错-Tsinghua University verilog operations, there are examples and the corresponding answers, as a very good practice