资源列表
Research_proj
- This document consists of the Latest reasearch concepts for the masters in vlsi
RS232capture
- This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file
dsp-with-FPGA--verilog_code
- FPGA DSP算法实现代码，做FPGA的非常值得看一看。-dsp with FPGA verilog code
DE0_NANO_GSensor
- Altera DE0-Nano 开发平台Gsensor传感器应用官方Demo。-Altera DE0-Nano the development platform Gsensor sensor applications Official Demo.
Four-bit-full-adder
- 四位全加器，是自己编写的，如有错误，请原谅-I have written four full adder, is subject to error, please forgive
vhdlvlogcompared
- VHDL与Verilog的比较-VHDL and Verilog comparison
CPLD_raoma
- 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选
counter2b
- 基于vhdl完成4位计数器功能的实现，并基于此程序完成16位加法器程序的编写，内附testbench,测试成功。-Based on the vhdl completed four counter function to achieve, and the completion of a 16-bit adder program written based on this program, enclosing testbench, the test is successful.
fpga_led
- Verilog入门例子，学会如何开发VERILOG程序-Verilog entry, how to develop VERILOG program to learn
Multiplier
- 4 bit multiplier 4 bit multiplier 4 bit multiplier-4 bit multiplier 4 bit multiplier 4 bit multiplier 4 bit multiplier
VHDL_clock
- VHDL电子钟,课程设计，时间可调，有闹钟，大小月，闰年，整点报时-a clock which is write in VHDL language