资源列表
Altera_Stratix_GX
- Protel99库 Altera_Stratix_GX-Library Altera_Stratix_GX Protel99
JPEG_verilog_code
- jpeg的verilog代码，只是编码部分的代码-jpeg of the verilog code, but coding part of the code
multipliers
- my file contain programns on D ,S-R,T, and counter programs
OFDMcode
- OFDM 的 VHDL 实现 分块实现. 功能强大
OFDMcode_VHDL
- 用matlab语言对ofdm的原理进行仿真，并配有多张仿真图
cnt12
- 基于VHDL的计数器控制程序，大三的时候写的，感觉不错。-VHDL-based counter control procedures, junior year writing, I feel good.
i2s_input
- 基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真-FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment
hdlc
- HDLC code in vhdl working code
_1_turn_on_led
- 通过开关控制led亮灭，板子为ep2c8q208板子-Led by light switch off, the board is ep2c8q208 board
VHDLjindianshili
- 37个经典的VHDL程序。有比较器、七段译码器、状态机等。
FPGA-frequency
- 本设计基于FPGA设计等精度频率计，并采用NIOS II控制液晶显示器显示测量频率。-The design is based on FPGA design precision frequency meter, and using NIOS II controlled LCD display shows the measured frequency.
MATLAB_sg_IP.rar
- 使用MATLAB为System Generator for DSP创建IP,The use of MATLAB for System Generator for DSP to create IP